Job Description

Lead verification Bangalore About company Ventana delivers the highest performance RISC-V CPUs with extensible instruction set capability delivered in the form of multi-core chiplets or core IP for high-performance applications in the cloud, enterprise data center, hyperscaler, 5G, edge compute, AI/ML and automotive markets.The well-funded start-up, founded by seasoned industry veterans, is currently hiring experienced professionals with backgrounds in Computer Hardware, spanning Architecture, Logic Design, Design Verification, and Performance Analysis and Tuning. We are seeking an experienced verification engineer to lead verification efforts of complex IP subsystems based on the open-source RISC-V architecture. The right candidate will have deep technical expertise combined with exceptional leadership skills. Responsibilities: Lead end-to-end verification of complex IP subsystems partnering with architecture and design teams Develop verification infrastructure components including test-benches, scoreboards, and stimulus generators Develop and execute comprehensive verification plans for units and features Implement functional coverage models Debug designs in simulation, prototyping platforms, and silicon Continuously drive methodology improvements to improve efficiency Mentor junior engineers to build a high performing team Minimum Qualifications: Bachelors or Masters degree in electrical, computer engineering or related field BS+8 years or MS+6 years of industry experience successfully delivering complex IP subsystems Skills Qualifications Required: SystemVerilog verification development experience Testbench construction using UVM or analogous methodologies Scoreboards and stimulus generators for complex units Strong background in industry standards and protocols such as PCIe, Ethernet, CXL, AMBA AXI etc., Unit or feature ownership throughout the project lifecycle Demonstrated team leadership experience with outstanding communication skills Highly motivated self-starter with strong execution mindset and collaborative approach Post-silicon debug experience strongly preferred Contact: Uday Mulya Technologies [email protected]