Synthesis Lead

Synthesis Lead

Experience: 7–12 Years

Location: Bengaluru

About the Role:

We are seeking a Synthesis Lead to drive RTL-to-Gate implementation for high-performance SoCs across advanced technology nodes. You will own synthesis, timing convergence, and optimization while working closely with Architecture, RTL, DFT, Physical Design, and STA teams to deliver world-class silicon.

What You'll Do

• Lead RTL synthesis for complex SoC and IP designs from RTL to gate-level netlist.
• Drive timing, area, and power optimization to achieve aggressive PPA targets.
• Develop and maintain synthesis flows, constraints, and automation.
• Collaborate with RTL, DFT, Physical Design, and STA teams to ensure seamless implementation and timing convergence.
• Perform timing analysis, resolve synthesis-related issues, and support ECO implementation.
• Debug synthesis QoR issues and optimize designs across multiple PVT corners.
• Mentor engineers and drive technical excellence across synthesis projects.

What We're Looking For

• 7–12 years of hands-on experience in ASIC RTL Synthesis.
• Strong expertise in Synopsys Design Compiler (DC) and/or Fusion Compiler.
• Solid understanding of SDC constraints, STA, Timing Closure, MMMC, OCV/AOCV/POCV, and synthesis optimization techniques.
• Experience with low-power design (UPF/CPF) and DFT-aware synthesis.
• Proficiency in Tcl, Perl, Python, or Shell scripting for flow automation.
• Strong understanding of ASIC implementation, RTL design principles, and advanced semiconductor technologies (5nm/7nm/12nm or below).

Preferred Qualifications

• Experience with high-performance CPU, GPU, AI/ML, Networking, or Automotive SoCs.
• Knowledge of Formal Equivalence Checking (LEC), CDC, and lint methodologies.
• Excellent problem-solving skills with the ability to lead cross-functional technical initiatives.