DFT Engineer
Actively Reviewing the ApplicationsNVIDIA
India, Telangana, Hyderabad
Full-Time
On-site
INR 1–1 LPA
Posted 3 weeks ago
•
Apply by May 29, 2026
Job Description
NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!
Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.
What You'll Be Doing
JR2012020
Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.
What You'll Be Doing
- As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression.
- Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features.
- In addition, you will help develop and deploy DFT methodologies for our next generation products.
- Be apart of innovation to strive improve the quality of DFT methods.
- You will also need to work with multi-functional teams to incorporate DFT features into the chip.
- Occasional travel and also some late hours online meetings involved during critical milestones.
- BSEE or MSEE from reputed institutions or equivalent experience.
- 3+ Years of experience preferably in Design for testability (DFT)
- You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design.
- Experience in RTL and Gates verification and simulation.
- You need to be familiar with BIST architecture and JTAG/IEEE1149.1/IEEE1500.
- Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
- Strong analytical and problem solving skills.
- Expert coding skills in industry standard scripting languages.
- Extraordinary written and oral communication skills with the curiosity to work on rare challenges.
JR2012020
Required Skills
Quick Tip
Customize your resume and cover letter to highlight relevant skills for this position to increase your chances of getting hired.
Related Job Recommendations
View All
Designer
89% matchTRACTEBEL
India
Full-Time
Engineering
Excel
Electrical
MBA Management Trainees(Marketing)_Freshers
94% matcheJAmerica
India
Full-Time
Data Analysis
Excel
PowerPoint
+2
Quality Engineer
93% matchCyient
India
Full-Time
Power BI
Excel
PowerPoint
+2
Perception Function Owner
77% matchExpleo Group
India
Full-Time
₹4–6 LPA
Object Detection
Computer Vision
LiDAR
Senior Associate – CFO Services
90% matchAlvarez & Marsal
India
Full-Time
Excel
Databases
Share
Quick Apply
Upload your resume to apply for this position