Verification CAD Engineer, Sr Staff

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

About the Role

We are looking for a highly experienced and technically driven Sr. Staff Verification CAD Engineer to join our Global SoC CAD (GCAD) team. In this role, you will be a methodology leader and technical anchor for Design Verification (DV) CAD, responsible for driving next-generation verification methodologies, UVM-based testbench infrastructure, and cutting-edge Agentic AI solutions for DV automation. You will work closely with DV engineers, IP teams, and AI/GenAI platform teams to shape the future of verification at scale.

Key Responsibilities

DV Methodology Leadership

• Define, develop, and drive DV methodologies across IP and SoC verification flows
• Own and evolve the UVM-based testbench architecture standards, guidelines, and best practices across multiple design teams
• Lead verification planning — test plans, checker plans, and coverage closure strategies from specification to sign-off
• Drive regression infrastructure improvements including debug automation, triage flows, and coverage analysis
  
  
  

Agentic Solutions in DV

• Architect and deploy Agentic AI workflows for DV use cases including:
• Spec → Testplan generation
• Checker Plan → SVA/SV-UVM code generation
• Regression debug and failure triage agents
• Stimulus generation using AI-assisted PSS/UVM flows
• Evaluate and deploy external GenAI tools (e.g., Synopsys.ai, Cadence JedAI/Verisium) for DV productivity
• Drive dataset creation for DV-specific fine-tuning of LLMs (assertions, drivers, monitors, coverage models)
  
  
  

CAD Tool & Flow Development

• Develop and maintain CAD tools and automation scripts supporting DV flows (Python, Perl, TCL, SystemVerilog)
• Enable and support Verification Compiler (VC), simulation tools (VCS, Xcelium), and formal tools (JasperGold, VC Formal)
• Drive emulation/prototyping CAD enablement (Palladium, Veloce) for pre-silicon validation acceleration
• Contribute to IPQA (IP Quality Assurance) flows and DV sign-off checklists
  
  
  

Cross-Functional Collaboration & Leadership

• Serve as a technical mentor and guide for Staff and Senior DV CAD engineers
• Partner with DV horizontals, IP teams, and SoC DV teams to align on methodology and tooling
• Represent the DV CAD team in program reviews, ops reviews, and cross-site technical forums
• Drive efficiency KPIs — regression TAT, coverage closure rate, bug escape metrics
  
  
  

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
  
  
  

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Required Qualifications

Area Requirements

Education B.E./B.Tech or M.E./M.Tech in Electronics / VLSI / Computer Engineering

Experience 12+ years in Design Verification / Verification CAD

DV Expertise, Deep expertise in SV-UVM testbench development, constrained random verification, functional coverage, SVA Scripting & Automation, Strong proficiency in Python, Perl, TCL, Makefile-based flows

Agentic/GenAI Experience or strong interest in LLM-based code generation, agentic workflows, RAG systems for DV

Tools: VCS / Xcelium, Verdi / DVE, Palladium/Veloce (preferred)

Methodology: Verification planning, coverage-driven verification, low-power verification, DFT verification

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