SoC Senior Design and Integration Engineer, Google Cloud

Job Description

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in ASIC/SoC development with Verilog/SystemVerilog. Experience in one or more SoC Integration domains and flows (Clocking or debug or fabrics/NoC or Security or low power methodologies). Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Preferred qualifications: Experience with programming languages (e.g., Python, C/C++ or Perl). Experience in SoC designs and integration flows. Knowledge of bus architectures, fabrics/NoC or memory hierarchies. Knowledge of high performance and low power design techniques. About The Job In this role, you?ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You?ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. The AI and Infrastructure team is redefining what?s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Responsibilities Own microarchitecture, implementation and integration of SoC chassis and subsystems. Perform quality check flows like Lint, CDC, RDC, VCLP. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams. Identify and drive Power, Performance and Area improvements for the domains owned. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .