Senior DFT consultant

Company Description BigEndian Semiconductors is a fabless semiconductor startup building secure, high-performance System-on-Chips (SoCs) in India for global markets. The company focuses on silicon platforms that power next-generation surveillance, telecom, IoT, and enterprise systems, driven by a “security by design” approach that tightly integrates hardware and software. With deep expertise in VLSI, system architecture, and embedded software, BigEndian develops trusted solutions for both national security and commercial applications. Headquartered in Bengaluru and supported by strategic partners in Taiwan and India, the company is led by industry veterans from Intel, ARM, Broadcom, and Zenoti, and is backed by government programs and deep-tech investors. BigEndian is committed to advancing India as a global hub for semiconductor design, innovation, and manufacturing.
Role Description The Senior DFT (Design for Test) Consultant will work on a temporary, remote basis, collaborating with design and verification teams to define and implement DFT strategies for complex SoCs. Day-to-day responsibilities include architecting scan, BIST (MBIST/LBIST), boundary scan, and test compression structures, and integrating DFT features into RTL and gate-level designs. The role involves generating and validating test patterns, performing fault coverage analysis, and optimizing testability while balancing area, power, and performance constraints. The consultant will review design specifications, conduct DFT design reviews, and provide guidance on industry-standard test methodologies, flows, and tools. The Senior DFT Consultant will also mentor team members, document best practices, and support silicon bring-up and yield improvement activities as needed.
Qualifications

• Strong proficiency in DFT architecture and implementation, including scan insertion, MBIST/LBIST, boundary scan (JTAG), and test compression techniques.
• Experience with EDA tools for DFT (e.g., Synopsys, Cadence, Siemens/Mentor) and familiarity with RTL/gate-level design flows.
• Solid understanding of digital design fundamentals, SoC integration, and VLSI concepts, including timing, synthesis, and physical design considerations for test.
• Hands-on experience with ATPG, fault modeling, coverage analysis, and pattern generation for high-volume manufacturing test.
• Background in semiconductor product engineering or silicon validation, including debug of test failures and yield optimization, is highly beneficial.
• Ability to collaborate effectively with cross-functional teams, communicate technical concepts clearly, and operate independently in a remote consulting environment.
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field; 8+ years of relevant DFT experience in complex ASIC/SoC projects preferred.
• Exposure to security-focused SoCs,