Memory (ASIC) Design Engineer

Employment Type: Full-time

Experience: 3–10+ years

Vicharak is an Indian semiconductor and computing company designing high-performance computing platforms, FPGA-based products, single-board computers, and next-generation edge AI processors.

We are developing a high-performance, energy-efficient edge AI accelerator focused on transformer and large-language-model workloads. Our work includes custom memory architectures, compute-in-memory, advanced data formats, high-bandwidth memory subsystems, and ASIC implementation on advanced semiconductor nodes.

We are looking for a Memory Design Engineer to work on custom SRAM, MRAM, register-file, and compute-in-memory macros for our next-generation AI accelerator.

The engineer will be responsible for memory-cell evaluation, array architecture, peripheral circuit design, characterization, verification, and integration of custom memory macros into the SoC.

The role requires a strong understanding of transistor-level circuit design, memory architecture, process variation, timing, power, reliability, and physical-design constraints.

• Design and optimize custom SRAM, register-file, and embedded-memory macros.
• Develop memory-array architectures, including bit-cell selection, banking, segmentation, redundancy, and power-domain organization.
• Design peripheral circuits such as:
• Sense amplifiers
• Write drivers
• Precharge circuits
• Row and column decoders
• Word-line drivers
• Level shifters
• Reference-generation circuits
• Read and write assist circuits
• Evaluate SRAM,gain-cell, and other emerging-memory technologies.
• Design memory structures suitable for digital and mixed-signal compute-in-memory architectures.
• Optimize memory macros for:
• Read and write latency
• Dynamic and leakage power
• Area and density
• Read stability
• Write margin
• Retention
• Endurance
• Perform transistor-level simulations using SPICE-based tools.
• Run PVT, Monte Carlo, mismatch, aging, and reliability analysis.
• Characterize memory macros and generate timing, power, and functional models.
• Develop Liberty, Verilog, LEF, GDS, and related views required for SoC integration.
• Work closely with architecture, RTL, physical-design, DFT, verification, and compiler teams.
• Support memory BIST, redundancy, repair, ECC, and production-test architecture.
• Perform post-layout simulation and analyze parasitic effects.
• Participate in design reviews, documentation, silicon bring-up, and post-silicon characterization.
• Work with foundry PDKs and memory-device models on advanced technology nodes.

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Microelectronics, VLSI, or a related field.
• Strong understanding of CMOS transistor-level circuit design.
• Experience designing SRAM, register files, MRAM, or other embedded-memory circuits.
• Knowledge of memory-cell stability and performance metrics, including:
• Static noise margin
• Read margin
• Write margin
• Retention voltage
• Read disturb
• Write failure
• Experience with SPICE-level simulation and characterization.
• Understanding of process, voltage, temperature, mismatch, and aging effects.
• Familiarity with custom layout, parasitic extraction, DRC, LVS, and post-layout verification.
• Understanding of memory timing, power, reliability, and test methodologies.
• Ability to debug complex transistor-level and mixed-signal design issues.
• Strong analytical, documentation, and cross-functional communication skills.

• Experience with SRAM compiler development or custom-memory macro generation.
• Experience with SRAM, ReRAM, gain-cell memory, or other emerging non-volatile memories.
• Experience with compute-in-memory or in-memory-compute architectures.
• Understanding of AI accelerator memory requirements and transformer workloads.
• Experience with low-voltage and high-performance memory design.
• Knowledge of assist techniques such as word-line boosting, negative bit-line, supply collapse, and source-line control.
• Experience with ECC, redundancy, repair, MBIST, and BIRA.
• Experience with advanced semiconductor nodes such as 7 nm, 5 nm, or below.
• Familiarity with Cadence Virtuoso, Spectre, Synopsys HSPICE, PrimeSim, Calibre, Pegasus, Liberate, or PrimeLib.
• Experience taking a memory macro from architecture through tapeout and silicon validation.
• Knowledge of Verilog, SystemVerilog, Python, TCL, SKILL, or other design-automation languages.

• High-bandwidth on-chip memory for an edge AI accelerator.
• Custom SRAM and emerging-memory macros.
• Compute-in-memory architectures for matrix and tensor operations.
• Ultra-low-power memory circuits for battery-operated AI systems.
• Memory architectures supporting low-precision formats such as FP8, FP4, INT4, and custom numerical representations.
• Silicon test chips and production-scale ASICs on advanced semiconductor nodes.

• Work on a semiconductor product being designed and developed in India.
• Contribute directly to the architecture of a next-generation edge AI processor.
• Work across device, circuit, architecture, and system levels.
• Take ownership of designs from initial concept through tapeout and silicon validation.
• Collaborate with experienced semiconductor engineers who have delivered multiple production tapeouts.
• Build technologies intended for real-world deployment in robotics, smart devices, and edge AI systems.

Candidates may apply by sharing their resume, relevant project details, publications, patents, or tapeout experience with Vicharak.

• Please include a short description of the memory circuits, macros, or semiconductor products you have previously designed.