Front-End Silicon Design & Integration Engineer

Actively Reviewing the Applications

AMD

India, Karnataka, Bengaluru Full-Time On-site

Posted 20 hours ago • Apply by June 4, 2026

Job Description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

Front-End Silicon Design & Integration (FEINT) Engineer

The Role

A Front-End Silicon Design and Integration (FEINT) Engineering role in our Security IP (SECIP) team, where a large number of embedded micro-processor subsystems, hardware accelerators and other IPs vital to improve system performance and functionality are designed and verified. These IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our FEINT engineers will perform RTL synthesis and PPA analysis in order to improve the QoR of RTL designs. They will also create, adopt and automate RTL static design rule checks, perform ECO and LEC checks, as well as support SOC integration of the IPs.

The Person

A talented FEINT engineer with strong records of technical ownership and execution to drive synthesis, PPA analysis, ECO, and static verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

Key Responsibilities

Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result)
Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies
Develop, adopt and automate RTL static design rule checks in collaboration with Back-End Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team
Develop and adopt FEINT design and verification infrastructure, methodology and tools

Preferred Experience

BSc with a minimum of 2 years relevant experience, or MSc with a minimum of 1 years
Proven understanding of RTL design, synthesis, and ECO principles
Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, etc.
Proficient with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile)
Excellent skills with Unix/Linux environment
Familiar with RTL coding techniques for competitive PPA-measured QoR
Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.)
Good understanding of gate level circuit design and physical level design concept and methodology
Familiar with VCS/Verdi and SPG based (dynamic/static) verification environments
Excellent communication skills (both written and oral)
Self motivated, and committed to achievement

Academic Credentials

Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or possibly a related field
Master's Degree preferred

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.