DFT Lead Engineer

Job Title

DFT Lead Engineer (ASIC / SoC)

Experience

10-15 Years

Location

Bengaluru

Employment Type

Full-time

Job Summary

We are looking for an experienced DFT Lead Engineer to lead and execute Design-for-Test (DFT) activities for advanced ASIC/SoC projects. The ideal candidate will own end-to-end DFT architecture, drive high test coverage, mentor junior engineers, and collaborate closely with design, physical implementation, and EDA vendors to ensure robust and manufacturable silicon.

Key Responsibilities

DFT Architecture & Implementation

• Lead and execute DFT activities for complex ASIC/SoC designs.
• Define and drive Scan ATPG architecture from specifications.
• Define and drive MBIST architecture from specifications.
• Optimize DFT implementation to meet coverage, quality, and schedule goals.
  
  

ATPG, Simulation & Debug

• Perform ATPG simulations and achieve maximum fault and test coverage.
• Analyze ATPG, scan, and MBIST failures and guide teams to debug and resolve issues.
• Ensure compliance with foundry requirements and pattern generation guidelines.
  
  

Automation & Optimization

• Develop and automate DFT scripts to improve productivity, reduce cycle time, and enable predictable execution.
• Optimize design for PPA (Power, Performance, Area) while maintaining test quality.
  
  

ECO & Post-Layout

• Handle ECO implementation related to DFT.
• Perform and support post-layout simulations and sign-off activities.
  
  

Leadership & Collaboration

• Mentor, train, and guide junior DFT engineers.
• Work closely with RTL, PD, verification, and manufacturing teams.
• Coordinate with EDA vendors and stay updated with the latest DFT tools, flows, and methodologies.
  
  

Required Skills & Qualifications

• 10-15 years of hands-on experience in DFT for ASIC/SoC designs.
• Strong expertise in Scan, ATPG, MBIST, and DFT sign-off flows.
• Experience with industry-standard DFT EDA tools (e.g., Synopsys, Cadence, Siemens).
• Solid understanding of fault models, coverage metrics, and debug methodologies.
• Experience with post-layout DFT validation and ECO handling.
• Strong scripting skills (TCL, Perl, Python or equivalent) for automation.
• Good understanding of foundry requirements and manufacturing test flows.
  
  

Soft Skills

• Strong technical leadership and mentoring capability
• Excellent problem-solving and debugging skills
• Effective communication and cross-team collaboration
• Ability to own and drive deliverables independently
  
  

Nice to Have

• Experience with advanced technology nodes
• Exposure to low-power DFT techniques
• Prior experience in leading DFT teams or acting as DFT owner for full chips