Design Verification Engineer
Actively Reviewing the ApplicationsTessolve
Job Description
Senior IP Design Verification Engineers (3+ to 8+ yrs)
Locations: Bhubaneswar
Company: Tessolve Semiconductor
Looking for experienced DV engineers with strong SystemVerilog + UVM skills and Experience in building a UVM test bench from scratch.
Must Have:
✔ 3+ to 8+ yrs years in IP Verification
✔ UVM TB development, SVA, coverage, debugging
✔ Experience with VCS/Questa/Xcelium/VCS, Verdi/DVE
✔ Scripting (Python/Perl/Shell/C/C++)
📩 Apply: [email protected]
Subject: Senior DV Engineer – Preferred Location
Quick Tip
Customize your resume and cover letter to highlight relevant skills for this position to increase your chances of getting hired.
Related Similar Jobs
View All
GenAI Full Stack Developer
Persistent Systems
Software Test Engineer (Database, DWH, ETL Testing, and Automation Test Framework)
Visa
Remote Data Scientist
Turing
Developer II - Software Engineering
UST
Senior Engineer Instrumentation
Reliance Industries Limited
Quick Apply
Upload your resume to apply for this position