Design for Test (DFT) Engineer

We are seeking experienced DFT Engineers with strong expertise in Scan, ATPG, and MBIST for SoC/ASIC designs. The role focuses on implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness.

Key Responsibilities

Implement and verify Scan, ATPG, and MBIST for complex SoCs.

Perform pattern generation, coverage analysis, and debug.

Integrate and validate MBIST with appropriate memory test algorithms.

Coordinate with RTL and Physical Design teams for smooth DFT integration and signoff.

Develop automation scripts to streamline DFT flows.

Required Skills

Minimum 4 years of DFT experience in ASIC/SoC environments.

Hands-on Expertise With EDA Tools Such As

Synopsys (DFT Compiler, TestMAX, TetraMAX)

Cadence Modus

Preferred: Experience with Siemens Tessent / FastScan.

Strong understanding of fault models (stuck-at, transition, path delay).

Knowledge of MBIST architecture and memory test techniques.

Scripting proficiency in TCL, Perl, or Python.

Familiarity with RTL design flows, STA constraints, and silicon bring-up

Skills: scan,dft,silicon,soc,soc/asic designs,asic design,mbist,automatic test pattern generation (atpg)